FIFO control and status
| EN | If 1: write result to the FIFO after each conversion. |
| SHIFT | If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. |
| ERR | If 1: conversion error bit appears in the FIFO alongside the result |
| DREQ_EN | If 1: assert DMA requests when FIFO contains data |
| EMPTY | |
| FULL | |
| UNDER | 1 if the FIFO has been underflowed. Write 1 to clear. |
| OVER | 1 if the FIFO has been overflowed. Write 1 to clear. |
| LEVEL | The number of conversion results currently waiting in the FIFO |
| THRESH | DREQ/IRQ asserted when level >= threshold |